1. Field of the Invention
The present invention relates to a decoding apparatus, and more particularly a decoding apparatus for decoding, for example, a variable-length encoded image.
2. Related Background Art
Among various methods proposed for high efficiency encoding, the so-called hybrid DCT method according to the CMTT/2 Recommendation 723 is known as the representative high efficiency encoding method in the field of images. Also B2 code is proposed as the variable-length codes for these encoding methods. These encoding methods and the B2 code are detailedly described by Y. Ohtsuka, "Encoding technologies for current television and HDTV", J. of Television Association, Vol. 45, No. 7, pp. 800-802(1991).
In said hybrid DCT method, for the non-zero coefficients and the zero-run value, the B2 code transmits expansion codes and information codes alternately, taking two bits as a pair, with an expansion code "0" as a partition (stop code). However the stop code is not transmitted only in case of the maximum code length. Also shorter codes are assigned to the non-zero coefficients and the zero-run value, in the descending order of the frequency of appearance thereof.
The B2 code has a feature that the expansion code and the information code have clear positions. If the expansion code is erroneous, there may result a phenomenon that a code appears as two codes or two codes appear as a code, but the error does not propagate to the next DCT block, as long as an EOB code, indicating that all the subsequent coefficients are zero to the end of the DCT block, is properly detected.
FIG. 5 shows an example of the B2 code, and FIG. 3 shows a conventional variable-length decoding circuit for decoding the codes which are variable-length encoded by the B2 code system.
Referring to FIG. 3, a data input terminal 121 receives data, in the form of a word of a predetermined bit width, including codes from two bits at minimum to the maximum code bit length, encoded in the B2 code system.
A terminal 122 receives the clock signal, and a data output terminal 123 releases the variable-length decoded data.
The B2 code data, entered from the data input terminal 121, are supplied to a shifter circuit 101, and are released therefrom with a shift to the leading bit of the B2 code. The shifter circuit 101 is provided with an input terminal S for the shift amount.
The output of the shifter circuit 101 is supplied to a terminal a of a look-up table (LUT) 102, of which a terminal b releases the B2 code length, while a terminal c releases non-zero (meaning quantized coefficient (including "0"))/zero-run mixed data, and a terminal d releases a non-zero/zero-run flag.
The B2 code length released from the LUT 102 and the cumulative bit number of the B2 code lengths, until the immediately preceding clock signal, stored in a register 104 are added in a adder 103, and the cumulative sum released therefrom is supplied to the terminal S of the shifter circuit 101.
When the non-zero/zero-run flag from the LUT 102 is at the H-level, the non-zero/zero-run mixed data from the LUT 102 are transmitted through an AND gate group 105 and released from the data output terminal 123.
When the non-zero/zero-run flag from the LUT 102 is at the L-level, the outputs from the data output terminal 123 are made all zero by the ABD gate group 105. In this case, the non-zero/zero-run mixed data indicate the zero-run value, which are subjected to bit invention in an inverter 106 and an addition of "1" in an adder 107, and are supplied to a terminal D of a counter 108.
In case the non-zero/zero-run flag, supplied to a terminal E thereof, is at the L-level, the counter 108 effects uncounting operation in response to the clock signal supplied to a terminal C. The output of the counter 108 is supplied to an end detector 109.
The output (zero period end flag) of the end detection circuit 109, the result of detection of the zero-run value "1" released from a "1" detector 110, and the non-zero/zero-run flag are subjected to logic summation in an OR gate 111, of which output is supplied to a terminal E of a register 104.
When said terminal E of the register 104 is at the H-level, the register selects a terminal A for input, and renews the cumulative bit number. When said terminal E is at the L-level, a terminal B is selected and the cumulative bit number is retained.
FIGS. 4A to 4G are timing charts showing the functions of the conventional variable-length decoding circuit.
Input data shown in FIG. 4B are encoded by the combination of non-zero/zero-run mixed data and non-zero/zero-run flag shown in FIG. 5, and encoded data shown in FIG. 6 can be decoded, by the variable-length decoding circuit shown in FIG. 3, with timings shown in FIGS. 4A to 4G.
However, the conventional configuration explained above has been associated with the following drawback.
In case the zero-run data vary to a value larger than the number of clock signals for processing the remaining DCT block, or the non-zero data vary to zero-run data, due to an error on the transmission channel prior to the detection of the EOB code, the error propagates to the next DCT block, in case of the conventional variable-length decoding circuit as shown in FIG. 3, whereby the decoded image is aberrated, for example in the position on the image frame.